Koppar

它能帮你做什么

我们还没有为它写通俗的介绍。下面是我们从注册中心读取到的事实。

• 连接方式: 在云端运行
• 传输方式: Streamable HTTP
• 分类: 设计、图片与音频
• 你需要填写：Authorization

安装

选择你使用的 AI 应用，然后复制设置。

你需要

• 在云端运行无需安装任何东西，通过互联网连接

你用的是哪个应用？

claude mcp add --transport http koppar https://app.koppar.ai/mcp --header 'Authorization: your-value'

{
  "mcpServers": {
    "koppar": {
      "url": "https://app.koppar.ai/mcp",
      "headers": {
        "Authorization": "your-value"
      }
    }
  }
}

{
  "servers": {
    "koppar": {
      "type": "http",
      "url": "https://app.koppar.ai/mcp",
      "headers": {
        "Authorization": "your-value"
      }
    }
  }
}

你的选择通过 Cookie 保存在这台设备上，无需账户。

需要你填写的值

• Authorization 机密 必填 HTTP header
  Bearer sc_… key from Settings → Design from your own AI agent at app.koppar.ai (free sign-up)

这些设置是根据作者在注册中心的条目生成的。如果 README 的写法不同，请以 README 为准。

它能做什么

工具名称和描述与服务器在 2026年11月7日 报告的完全一致。这些内容由作者撰写，不是我们写的；我们以纯文本形式显示。

• get_workflow_guide

  How to drive Koppar end to end, and the instructions for each stage you do yourself: "research" (part research and the dossier), "synthesis" (writing the SKiDL schematic), "review" (design review), "board" (the board plan). Read the stage guide before doing that stage.

• create_design

  Start a new design from the user's brief (what the board must do, its interfaces, power, size and constraints). Returns the design_id every other tool takes and the web_url where the user follows the design. Uses no generation quota: the work is done by you.

• leave_feedback

  Send the Koppar team feedback from the user: about Koppar in general, or about one design (design_id). A rating from 1 to 5, a message, or both. Use it when the user asks you to pass something on, or tells you what worked or did not; say in the message what happened, in their wor

• list_designs

  The user's designs, newest first, including ones made in the web app (an agent can continue those too) and board workspaces (kind "board workspace"). With trashed, the designs in the trash instead.

• delete_design

  Move a design (or a board workspace) to the trash: it leaves list_designs and the web app, and restore_design brings it back. permanent deletes it with no trash to restore from. Refused while a run on it is in progress. The CLI: `koppar delete `.

• restore_design

  Put a deleted design back from the trash.

• get_design

  Where a design stands: the brief, the schematic (accepted or the last blocking error, ERC, part and net counts, submissions), the board run, the readable files, and the next step.

• search_kicad_symbol

  Search KiCad's standard symbol libraries for parts whose name contains a substring. Use this whenever you are not 100% sure the (library, name) pair you're about to pass to Part(...) exists. Always prefer the package-suffixed variant the search returns over a generic name. If a p

• get_kicad_symbol

  Return the full pin list (number, name, electrical type) and description for a specific KiCad symbol. For some high-risk power parts it also returns curated topology_constraints from datasheet-style application notes and footprint_suggestions. Use this before writing pin connecti

• search_kicad_footprint

  Search KiCad's standard footprint libraries. Returns 'Library:Footprint' strings suitable for the footprint= argument of Part(...). Query with the package family and pin count ('LGA-14', 'QFN-24', 'SOIC-8'), optionally a body size or pitch. When no name contains every word, near_

• create_custom_symbol

  Register a connectable schematic symbol for a part that is NOT in KiCad's libraries (search_kicad_symbol returned nothing). Use this for specialty ICs — LED-matrix drivers, niche sensors, etc. — INSTEAD of telling the synthesizer to model the part with discrete passives (which le

• add_custom_footprint

  Give the design a footprint of your own: a KiCad .kicad_mod (the file's text) for a package KiCad's libraries lack. It joins the design's "custom" footprint library and is used as "custom: ": pass that to create_custom_symbol (footprint=) or name it in the SKiDL script's footprin

• save_dossier

  Store the research dossier (markdown with ## Parts list, ## Power rails, ## Topology constraints, ## Notes, as the research guide describes). The verified pin tables from your lookups on this design are appended, and verified entries the design already had for parts you did not l

• submit_circuit

  Compile and check a complete SKiDL script: the symbol and footprint pre-flight (unambiguous typos are corrected and listed), SKiDL, the ERC score, KiCad ERC, floating subsystems, parts without a footprint, and supplier sourcing. Returns accepted plus blocking findings to fix and

• edit_circuit

  Apply SEARCH/REPLACE patches to your latest script and re-run every check, as submit_circuit does. The latest script is your last submission when it was sent back (attempt_N_circuit.py), otherwise the design's circuit.py. Each search must match the current file exactly once (whit

• read_design_file

  Read a text file of the design: prompt.txt (brief), dossier.md, circuit.py, circuit.net, result.json, circuit.erc.json (KiCad ERC violations), attempt_N_circuit.py / attempt_N_error.txt, board_plan.json, pcb_result.json, pcb_run.log, circuit.drc.json (KiCad DRC), netclasses.resol

• get_review_packet

  Everything a design review needs in one text: the brief, the dossier, circuit.py and the compiled connectivity (every net with every pin and its function), with the reviewer instructions. Review it yourself and fix blockers with edit_circuit.

• get_board_context

  What the board plan is decided from: the computed minimum board, BOARD STATS (pad density, fine-pitch parts, fanout), the parts and nets, board instructions the user gave, and the plan schema with its rules. Needs an accepted schematic.

• start_board

  Start place and route with your board plan (the JSON object from the board guide: board, stated, edge, chain, groups, near, side, fixed, keepouts, netClasses). The plan is clamped and returned as applied. Runs for minutes in the background: follow it with get_board_status. Needs

• get_board_status

  The board run: stage, size, layers, placement, routing completion, open nets, DRC counts; once finished, DRC violations by type, whether the fab files are released and, when not, the diagnosed causes (first = fix first: parts that did not fit, collisions, missing footprints, open

• get_bom

  The live-priced BOM: each line with references, value, footprint, the chosen offer (seller, part number, MPN, price, stock, match quality), alternatives and totals. refresh asks the sellers again (tens of seconds).

• choose_bom_part

  Pick which offer a BOM line uses: the line's references and a seller part number or MPN from its offer or alternatives in get_bom; null goes back to the automatic pick. Sourcing only: a different component is a circuit change.

• consolidate_bom_basic

  Move every resistor, capacitor and inductor bought outside JLCPCB's basic library onto an in-stock basic-library part of the same value, package and (capacitors) at least the same voltage rating. Each part outside that library adds a loading fee to a JLCPCB order, usually more th

• get_fab_status

  Whether the board has earned its fab files (zero serious DRC errors, nothing unconnected), and if not, why not.

• list_order_providers

  The PCB and assembly providers, whether each can quote and take this kind of board today, and what a handoff sends them.

• get_order_price

  One price for a quantity: parts from the sellers, the board and assembly from the chosen provider's quote, setup fees, and what the total does not include.

• send_order_to_provider

  Upload the released board (Gerbers, BOM, placement) to a manufacturer and return the page where the user pays. This publishes the design to a third party: call it only when the user has explicitly asked to order from that provider, and set user_confirmed only then. Some providers

• upload_board

  Replace the design's board with a .kicad_pcb you routed or edited yourself (the file, base64). The board must carry the design's circuit: every schematic part by reference, every pad on the net the netlist gives it; a footprint swap is allowed and recorded. Anything else is refus

• get_downloads

  Download URLs for the design (KiCad project, schematic, netlist, BOM CSV, board file, 3D model, Gerbers, order bundle) and which are available now. They take the same Authorization: Bearer API key; the CLI fetches them with `koppar download `.

• import_kicad_project

  Bring an existing KiCad project in as a board workspace: the project folder as a ZIP (the .kicad_pcb, .kicad_pro, schematics, footprint and 3D-model folders), base64-encoded, up to about 18 MB zipped. The CLI does this with `koppar import `. Or from_design_id: the KiCad project o

• get_board_info

  The board as it stands: copper layers, outline, design rules and net classes, counts (footprints, nets, tracks, vias, zones, keepouts, KiCad unconnected items), zones and keepouts, and every footprint with reference, value, footprint, position (origin, mm), rotation, side, locked

• place_footprints

  Put footprints exactly where given: KiCad board coordinates of the footprint origin in mm (y grows downward), rotation in degrees as KiCad shows it, side F or B (changing side flips the footprint, as KiCad does), locked. dx_mm/dy_mm/drot_deg move relative to where it is. Nothing

• auto_place

  Pack footprints inside the board outline with Koppar's heuristic placer (ratsnest-driven, courtyard-legal). By default every unlocked footprint moves and locked ones stay; refs names exactly which move (all others stay). Constraints: fixed (exact origin positions and rotation, ne

• anneal_place

  Dense placement by simulated annealing: wirelength inside the outline with courtyard gaps, edge connectors held on their edge, fixed and locked parts held, keepout rectangles kept clear (routing corridors), and a per-pad price for the bottom side (flip_cost, mm of wirelength; eac

• set_board_outline

  Replace everything on Edge.Cuts with a new outline: rect (optionally with corner_radius_mm), a polygon of points, or fit_to_parts (the rectangle around every footprint courtyard plus margin_mm). Give exactly one.

• set_design_rules

  Set the project design rules (.kicad_pro) and copper layer count. Works on a board workspace and on a generated design (create_design → start_board). On a generated design the rules go into circuit.kicad_pro/.kicad_dru in place (the previous ones are snapshotted under rules_revis

• set_keepouts

  Add or remove keepout rule areas. Each keepout is a rect or polygon on the given copper layers (default all) and forbids what it names: no_tracks, no_vias, no_zone_fills (all three default true), no_pads, no_footprints. route_board keeps tracks and vias out of them and KiCad DRC

• check_net_rules

  Check the copper against the project's net classes and differential pairs, which KiCad's DRC does not: every class or pair net's narrowest track and the length below its class width, and every pair (X_P/X_N, X+/X-, CAN X_H/X_L) with its coupled share at the class's diff_pair_gap,

• check_physics

  Judge the copper by physics, which KiCad's DRC does not: impedance from the stackup on controlled nets, IR drop and heating on rails with a stated current, pair and lane skew, a ground via beside every high-speed layer change, 3W spacing between high-speed runs, and the via path

• set_zones 看起来像是对 AI 下的指令

  Add or remove copper zones (pours). Each zone pours its net on the given copper layers over rect or polygon, by default the whole board outline. priority orders overlapping zones (higher fills first); clearance_mm and min_thickness_mm override the rules; thermal false connects pa

• add_copper

  Lay exact copper by hand where the routers leave a gap: tracks as polylines on one copper layer, and through vias. width_mm, diameter_mm and drill_mm default to the board's current track and via sizes. Nets must exist on the board. Nothing is checked here: run_drc afterwards, and

• prune_vias

  Remove every via the board does not need: groups of vias come out, the zones are refilled and KiCad's unconnected count compared, and a via stays only if removing it disconnects something. nets limits the candidates (GND and the plane rails first: pours already join most of their

• set_silkscreen

  Take clutter off the silkscreen. values "hide" (default) hides value and part-number fields; references "keep" (default), "fab" (moved to the fabrication layer) or "hide"; texts "fab" moves footprint texts off the silkscreen. run_drc's silk_overlap and silk_over_copper warnings c

• route_board

  Route under the project's rules and net classes. By default (no nets, no router, none of the single-route options below) it runs the full route pipeline Koppar benchmarks: the learned router on the whole board racing the negotiated router on a copy (the board with fewer open item

• repair_board

  Keep the copper of every net it already connects and route the nets still open around it: route_board with preserve_existing. The learned router service by default; router "ts" for the local router, which also keeps partial copper and runs its last-chance welds and plane-island b

• ripup_routing

  Delete tracks and vias: of the given nets, on the given layers (vias are not layer-filtered), with an end inside region, or all. Filters combine. tracks/vias choose which kinds (both by default); zones also deletes the copper zones (pours) the same filters match (a zone inside re

• cleanup_board

  Sweep the routing: zero-length and duplicate tracks, stub tracks (a free end, and everything the track touches stays joined without it), and vias that meet their net on fewer than two layers. Contact is copper overlap, as KiCad judges it. Refills the zones first so pours count as

• add_project_files

  Unpack a ZIP into the project folder, keeping its paths: new footprints into a .pretty library the fp-lib-table names, 3D models, a library table. Existing files are kept unless overwrite is true; the reply lists written, replaced and kept files. Base64, up to about 18 MB zipped.

• swap_footprint

  Replace footprints in place with another footprint from a library in the project's fp-lib-table (library:name): the reference, value, position, rotation (or rot_deg), side, lock and schematic link stay, and nets move pad by pad. pad_map maps a NEW pad number to the OLD pad whose

• fill_zones

  Refill every copper zone with KiCad's zone filler.

• stamp_silkscreen

  Silkscreen stamps for release, both off unless asked for: a small spec badge ("routed with Koppar", optionally the title, revision and part count) in the largest free patch of the front or back silk, and JLCPCB's JLCJLCJLCJLC placeholder on the back silk so their order number is

• tie_rail_pads

  Tie neighbouring same-net SMD pads of the plane nets (GND, the rails with a pour) together on their own layer with short tracks, so a group shares one via to the plane instead of one via per pad, as a designer does. A tie is placed only where it misses every other net's pad, its

• widen_nets

  Grow the tracks (and optionally vias) of the named nets in place, each as wide as its clearance to every other net's copper, holes and the board edge allows, up to the net's target width. Nothing moves and no via is added, so the score does not change. Routers neck power down to

• finish_board

  Close what the router left open the way a designer does: for each open net the diagnosis names the copper boxing it in; that copper is ripped (never a poured net), the open nets are routed FIRST into the space, then the ripped nets go back around them; up to `rounds` rounds, each

• bridge_islands

  A filled pour cut into islands by routing: one through-via per island that KiCad finds cut off from its net, placed well inside the island and inside the net's main copper on another layer, clear of every other net between. Reports the islands it found no site for. Run run_drc af

• tidy_copper

  After routing: every run redrawn as the fewest 0/45/90-degree segments that clear, and every track narrower than its net's netclass width widened where it fits (slid sideways, bumped around a lone obstacle, or necked only over the stretch that needs it; a via or thin track of ano

• polish_vias

  After route_board and prune_vias: rip one net at a time, most vias first, route it alone around everything else at a high via price, and keep the new copper only when KiCad counts fewer vias with no new open item or DRC error (a reroute that cuts a pour into islands first gets on

• couple_pairs

  After route_board: re-route the weakly coupled differential pairs one at a time, least coupled first. Both legs are ripped and routed alone around everything else as a pair; the new copper stays only when the pair's coupled share rises by min_gain_pct, its skew stays within max_s

• diagnose_open_nets

  For every net still open (or the nets named): each pad with the escape corridors free on its own layer, whether a via can be dropped beside it at all, and what blocks it (which part's pads, which net's tracks or vias, the board edge). A pad with no free corridor and no via site i

• run_drc

  KiCad's DRC on the board as it is now, with schematic parity when the project has its schematic: error and warning counts by type, shorts, unconnected items, parity items, and the first violations with their items and positions (types filters, max_violations caps; default 40). Al

基础检查i

我们检查的是任何人都能看到的信息；我们没有阅读代码。不适用的检查项不计入总数。 · 检查于 2026年11月8日

• ! 注意

  作者与仓库一致

  注册中心没有列出源代码仓库，因此无法将发布者（koppar.ai）与代码对应起来

• … 尚未检查

  仍在维护

  我们还没有从 GitHub 读取这个仓库

• … 尚未检查

  有许可证

  我们还没有从 GitHub 读取这个仓库

• ✓ 通过

  端点有响应

  在 687 毫秒内响应（HTTP 200）

• – 不适用

  使用 OAuth 登录

  无需登录

• ✕ 未通过

  工具描述中没有隐藏指令

  有 1 个工具描述包含看起来像是对 AI 下指令的文字。安装前请先阅读下方的内容

与“设计、图片与音频”中的其他服务器比较i

• 星标数多于此分类中其他 2757 个服务器的 0%
• 发布到注册中心的时间比此分类中其他 2757 个服务器的 59% 更新
• 基础检查结果等于或优于此分类中其他 2757 个服务器的 24%

与注册中心里这个分类中所有活跃的服务器比较。只有当发布者拥有该仓库时，星标数才计入。

替代选择

同一分类中其他作者的服务器，按星标数排序。

如何看卡片：★ GitHub 星标i三大支柱：评价 · 检查 · 使用情况i更新 = 最新版本发布到注册中心的时间i

作者的 README

仓库中没有找到 README