Vivado Red MCP

vivado-red-mcp — Vivado MCP server, Red Pitaya edition

An MCP server that lets an AI assistant such as Claude drive AMD/Xilinx Vivado directly: create projects, build block designs, synthesize, implement, simulate, read timing/utilization reports and generate bitstreams — without opening the Vivado GUI.

It has first-class support for the Red Pitaya STEMlab 125-14 (Zynq xc7z010clg400-1): you can go from a natural-language description to a .bit.bin running on the board, using either pure RTL or the official RedPitaya-FPGA PS+PL (ARM + FPGA) backbone, and deploy it over SSH.

Forked from coreyhahn/vivado_mcp and

heavily extended (93 tools): block design / IP Integrator, IP catalog, Hardware

Manager, advanced reports, Red Pitaya RTL and PS+PL flows, SSH deploy.

Current version: 0.5.0 — see What's new and CHANGELOG.md.

Not to be confused with the unrelated vivado-mcp package on PyPI. This project is

vivado-red-mcp: Python module vivado_red_mcp, command vivado-red-mcp.

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Contents

• What it can do
• Tested with
• Requirements
• Installation
• First steps
• Red Pitaya
• What's new in 0.5.0
• Troubleshooting
• Available tools
• Architecture
• License

What it can do

• Persistent Vivado session — one Vivado process in Tcl mode is kept alive, so commands don't pay the 20–30 s startup each time.
• Projects and design flow — create/open projects, add HDL and XDC files, synthesis, implementation, bitstream, run strategies.
• Block design (IP Integrator) — ports, IP cores, RTL module cells, nets, PS7 presets, validation, wrapper generation.
• Reports — timing (WNS/TNS/WHS/THS), utilization, clocks, power, DRC, methodology, QoR; returned as parsed values, not just raw text.
• Simulation (xsim) — behavioral and post-synthesis/implementation, read signal values, breakpoints.
• Red Pitaya — one-shot RTL build, full PS+PL build from the official RedPitaya-FPGA repo, bundled board constraints, .bit.bin generation, SSH deploy.
• Raw Tcl — anything not covered by a tool can be run as Tcl (multi-line scripts supported).

Tested with

The RedPitaya-FPGA tutorials in prj/Examples (Led_blink, Knight_rider, Stopwatch, Frequency_counter) build to a bitstream through the server. Led_blink and Knight_rider rebuilt from scratch with MCP tools only produce byte-identical bitstreams to the tutorials' own scripts.

Requirements

1. Python 3.10+
2. AMD Vivado (the free edition is enough for the Red Pitaya xc7z010). When installing, you only need *Vivado* and, under devices, *SoCs → Zynq-7000*; Vitis Model Composer and DocNav are not needed.
3. A Vivado license file — also for the free edition on 2025.x/2026.x. Without it Vivado refuses to start (a valid license was not found):

• open the Vivado License Manager ( /bin/vlm.bat on Windows, vlm on Linux);
• *Obtain License* → on the AMD site tick Vivado Basic Tier License, Node Locked License (no charge, no expiry) → *Generate Node-Locked License*;
• host ID: the MAC address of your network card (shown under *View Host Information*). The license is tied to the PC, not to the network you use;
• load the received Xilinx.lic with *Load License → Copy License*.

1. Vivado reachable by the server, either:

• on PATH (Linux: source /settings64.sh; Windows: add \bin to PATH), or
• by telling Claude the full path, which it passes to start_session (e.g. C:\AMDDesignTools\2026.1\Vivado\bin\vivado.bat).

pexpect (Linux/macOS) or pywinpty (Windows) is installed automatically.

Installation

1. Get the code and install it

git clone https://github.com/sinemortal/vivado-red-mcp.git

cd vivado-red-mcp python -m venv .venv

Windows: .venv\Scripts\activate

Linux/macOS: source .venv/bin/activate

pip install -e .

pip pins the MCP SDK to 1.x by itself. Do not upgrade mcp to 2.x: the server would not start ('Server' object has no attribute 'list_tools').

2. Register it with Claude Code

Once, for all your projects:

claude mcp add --transport stdio --scope user vivado -- vivado-red-mcp

If vivado-red-mcp is not on PATH when Claude Code starts (typical with a virtual environment), point to the venv's Python instead:

# Windows

claude mcp add --transport stdio --scope user vivado -- "C:\path\to\vivado-red-mcp\.venv\Scripts\python.exe" -m vivado_red_mcp

Linux/macOS

claude mcp add --transport stdio --scope user vivado -- /path/to/vivado-red-mcp/.venv/bin/python -m vivado_red_mcp

Or share it with a single project through a .mcp.json at the project root:

{

"mcpServers": { "vivado": { "type": "stdio", "command": "vivado-red-mcp" } } }

Check it with claude mcp list: vivado should show as connected.

3. Optional: disable the RedPitaya-FPGA auto-download

On startup the server downloads the RedPitaya-FPGA repo (source zip) into its working directory if it is missing, for the PS+PL flow. Set the environment variable VIVADO_MCP_NO_AUTOFETCH=1 to turn this off; the rp_fetch_repo tool can still download it on demand.

First steps

Talk to Claude in plain language, for example:

1. "Start a Vivado session" (add the path if Vivado is not on PATH)
2. "Open my project at C:/work/my_proj/my_proj.xpr"
3. "Synthesize and implement it, then tell me if timing is met"
4. "Show me the resource utilization"
5. "Generate the bitstream"
6. "Stop the Vivado session"

Claude picks the tools; you never have to call them by name.

Red Pitaya

Two flows, depending on whether you need the ARM processor:

Example prompt:

Make an LED blinker at 1 Hz for the Red Pitaya using the 125 MHz ADC clock on

led_o[0], build it and give me the .bit.bin.

To load the result on the board, ask Claude to use deploy_to_redpitaya (SSH, default credentials root/root; works with OS 1.04 xdevcfg and OS 2.00 fpgautil), or copy it yourself:

scp led_blinker.bit.bin root@rp-xxxxxx.local:/tmp/

ssh root@rp-xxxxxx.local 'cat /tmp/led_blinker.bit.bin > /dev/xdevcfg'

PS+PL and the RedPitaya-FPGA repo. The current upstream master targets Vivado 2025.1; older checkouts targeted 2020.1. Both layouts are supported. rp_setup_workspace copies the repo into a separate workspace and patches only that copy, so the scripts run on the Vivado you have installed (their exported block-design/IP scripts otherwise refuse any other release) and without a git checkout. Your downloaded repo is never modified. Details: get_vivado_doc redpitaya_ps_pl_flow.

Bundled board data (data/boards/):

• red_pitaya_125_14_full.xdc — full pinout (ADC, DAC, LEDs, expansion connector, XADC), port names as in the official red_pitaya_top (adc_dat_ich, dac_dat_o, exp_p_io, …); checked pin by pin against upstream sdc/red_pitaya.xdc.
• red_pitaya_125_14_leds_min.xdc — 125 MHz differential ADC clock + 8 LEDs, for hello-world designs.
• red_pitaya_125_14_info.json — part number and board metadata.

The RedPitaya tutorials (prj/Examples) use different port names (adc_dat_a_i, adc_clk_p_i, …) and a PS7 preset (cfg/red_pitaya.xml); use their own cfg/ files when rebuilding them.

More Italian prompt examples and the step-by-step low-level flow: USAGE.md.

What's new in 0.5.0

Renamed to `vivado-red-mcp` (package, Python module vivado_red_mcp, command vivado-red-mcp), so it no longer clashes with the unrelated vivado-mcp package on PyPI. If you installed an earlier version, reinstall it and re-register it with Claude Code using the new command (see Installation).

0.4.0

Works on Vivado 2026.1 and with the current RedPitaya-FPGA repo.

Fixed:

• Server failed to start with MCP SDK 2.x → SDK pinned to 1.x.
• Simulation never worked when the server was started by Claude Code on Windows (xsim: Spawn failed) → fixed.
• Multi-line Tcl sent through run_tcl was silently corrupted on Windows → fixed.
• get_timing_summary always returned empty values; get_utilization misread newer reports → both parse current Vivado output.
• Reports right after a build failed with no message (No open design) → the latest completed run is opened automatically.
• get_synthesis_errors_parsed always returned 0 errors → now reads the run logs, including failed IP runs.
• launch_simulation modes rejected by recent Vivado → fixed.
• generate_bitstream timed out after 300 s and didn't check the result → now verified, returns the .bit path.
• Missing license (or any startup failure) now reports Vivado's own message in seconds instead of a generic error after 2 minutes.
• Bundled `red_pitaya_125_14_full.xdc` had 6 wrong pins (ADC channel A MSB and dac_dat_o[8..12]) → corrected.
• PS+PL flow broken by the new RedPitaya-FPGA layout → both layouts supported.

New tools: create_bd_port, add_module_to_bd, configure_bd_cell, set_run_strategy. Full list in CHANGELOG.md.

Troubleshooting

Available tools

Session management

• start_session - Start a persistent Vivado Tcl session (optional vivado_path)
• stop_session - Stop the Vivado session
• session_status - Session statistics
• check_session_health - Detect a hung/dead session, optionally recover

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